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specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 71807 ti pc b8-7592, no.0646-1/24 LA73033M overview this LA73033M is dvd recorder video signal input sw & output driver. functions [sw side] ? composite signal five-input sw and s signal three-input sw ? keyed clamp ? component signal or rgb signal 1 input ? 0db/ 6db amplifier ? agc amplifier (composite and y signal only) ? lpf for removal of 13.5mhz clock ? composite output/ y output changeover switch ? compatible with standby (two types) ? c.sync & v.sync output [driver side] ? six-channel input & six-channel output of composite signal & s signal & component or rgb signal ? clamp (keyed clamp for cb and cr) ? 6db/ 9db amplifier amplifier ? lpf for removal of 27mhz/ 54mhz clock ? output mute (three types) ? 75 driver (two drives possible) ? through changeover of rgb signal from the sw side ? y/ c-mix ? dc output for s1/ s2 ? scart-rgb/ yc changeover sw orderin g numbe r : ena0646 monolithic linear ic i 2 c bus control (excluding standby control and rgb through control)
LA73033M no.a0646-2/24 specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 7.0 v allowable power dissipation pd max ta 75c * mounted on a board 1200 mw operating temperature topg -20 to +75 c storage temperature tstg -40 to +150 c * mounted on a board : 114.3 76.1 1.6mm 3 , glass epoxy board. recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc 5.0 v operating supply voltage range v cc opg 4.75 to 5.25 v input pin voltage application range v in v cc opg +0.3 7v -0.3 to v cc opg +0.3 v package dimensions unit : mm (typ) 3255 sanyo : qfp80(14x14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.25 0.65 (0.83) (2.7) 0.8 1 20 21 40 41 60 80 61
electrical characteristics at ta = 25 c, v cc = 5.0v input signal out spec control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit r1 v18 v38 v30, v35 sw1 sw2 current drain 1 i cc 11 v cc 1 current flowing through v cc 1 at no signal 58 73 88 ma 330 0 0 3.5 01000010 00000000 current drain at standby i cc 12 v cc 1 current flowing through v cc 1 at standby control 9 11 13 ma 330 3 0 current drain 1 at rgb standby i cc 13 v cc 1 current flowing through v cc 1 at ext-rgb control 11 14 17 ma 330 3 3 01001010 00000000 01101010 00000000 10001010 00000000 10101010 00000000 composite output clamp voltage c23 v in 13 v in 15 v in 17 v in 19 v in 21 sg3 1vp-p t27 measure the output clamp voltage (sink chip voltage) 0.7 0.8 0.9 v 330 0 0 3.5 11001010 00000000 01000100 00000000 01100100 00000000 chroma output center voltage c25 v in 7 v in 5 v in 3 sg2 714mvp-p t25 measure the output dc voltage (center voltage) 2.2 2.4 2.7 v 330 0 0 3.5 10000100 00000000 01000100 00000000 01100100 00000000 y output clamp voltage c27 v in 79 v in 77 v in 75 sg1 1vp-p t27 measure the output clamp voltage (sink chip voltage) 0.7 0.8 0.9 v 330 0 0 3.5 10000100 00000000 component output pedestal voltage pc23 pc25 v in 1 v in 11 v in 9 sg5 sg6 sg6 1vp-p 1vp-p 1vp-p t23 t25 measure the output pedestal clam p voltage 2.4 2.5 2.6 v 330 0 0 3.5 00000100 00000000 rgb output clmap voltage rc23 rc25 rc29 v in 11 v in 9 v in 1 v in 73 sg8 sg8 sg5 sg8 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t29 measure the output pedestal clamp voltage 1.15 1.25 1.35 v 330 0 0 3.5 00100100 00000000 01001010 00000000 01000100 00000000 g23h g25h g27h v in 13 v in 7 v in 79 sg5 sg6 sg5 1vp-p 714mvp-p 1vp-p t27 t25 t27 0 0 3.5 01001000 00000000 gain at 6db g23h g25h g27h g29h v in 11 v in 9 v in 1 v in 73 sg8 sg8 sg5 sg8 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 measure gain for input of each output 5.5 6 6.5 db 330 0 0 3.5 00101100 00000000 continued on next page. LA73033M no.a0646-3/24
continued from preceding page. input signal out spec control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit r1 v18 v38 v30, v35 sw1 sw2 01000010 00000000 01000000 00000000 g23l g25l g27l v in 13 v in 7 v in 79 sg5 sg6 sg5 2vp-p 1.428vp-p 2vp-p t27 t25 t27 01000000 00000000 gain at 0db g23h g25h g27h g29h v in 11 v in 9 v in 1 v in 73 sg8 sg8 sg5 sg8 1.4vp-p 1.4vp-p 2vp-p 1.4vp-p t23 t25 t27 t29 measure gain for input of each output -0.5 0 0.5 db 330 0 0 3.5 00100000 00000000 va23m 01001010 10000000 agc-amp control voltage va23m va27m v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t27 t27 measure v30 and v35 where the output gain changeable. 2 3.5 5 v 330 0 0 va27m 01001000 10000000 01001010 00000000 01000100 00000000 f23 f25 f27 v in 13 v in 7 v in 79 sg3 sg2 sg1 10mhz 10mhz 10mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01001000 00000000 10mhz change rate for f characteristics of gain f23 f25 f27 f29 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 10mhz 10mhz 10mhz 10mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 measure gain for input of each output and calculates the change rate for gain at 100khz. -0.5 -0.1 0.5 db 330 0 0 3.5 00101100 00000000 01011010 00000000 01010100 00000000 f23l1 f25l1 f27l1 v in 13 v in 7 v in 79 sg3 sg2 sg1 4.5mhz 4.5mhz 4.5mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01011000 00000000 4.5mhz change rate of f characterics of gain (with lpf) f23l1 f25l1 f27l1 f29l1 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 4.5mhz 4.5mhz 4.5mhz 4.5mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 measure gain for input of each output and calculates the change rate for gain at 100khz. -0.5 -0.2 0.5 db 1k 0 0 3.5 00111100 00000000 01011010 00000000 01010100 00000000 f23l2 f25l2 f27l2 v in 13 v in 7 v in 79 sg3 sg2 sg1 5mhz 5mhz 5mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01011000 00000000 5mhz change rate of f characterics of gain (with lpf) f23l2 f25l2 f27l2 f29l2 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 5mhz 5mhz 5mhz 5mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 measure gain for input of each output and calculates the change rate for gain at 100khz. -1 -0.3 0.5 db 1k 0 0 3.5 00111100 00000000 continued on next page. LA73033M no.a0646-4/24
continued from preceding page. input signal out spec control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit r1 v18 v38 v30, v35 sw1 sw2 01011010 00000000 01010100 00000000 f23l3 f25l3 f27l3 v in 13 v in 7 v in 79 sg3 sg2 sg1 13.5mhz 13.5mhz 13.5mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01011000 00000000 13.5 mhz change rate of f characteristics of gain (with lpf) f23l3 f25l3 f27l3 f29l3 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 13.5mhz 13.5mhz 13.5mhz 13.5mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 measure gain for input of each output and calculates the change rate for gain at 100khz. -41 -30 db 1k 0 0 3.5 00111100 00000000 01001010 00000000 01000100 00000000 h23 h25 h27 v in 13 v in 7 v in 79 sg3 sg2 sg1 5mhz 5mhz 5mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01001000 00000000 output drive capacity 1 (secondary distortion) h23 h25 h27 h29 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 5mhz 5mhz 5mhz 5mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 connect the load of 330 to the output via c connection and measure the secondary distortion of output. -45 -35 db 330 0 0 3.5 00101100 00000000 01011010 00000000 01010100 00000000 h23 h25 h27 v in 13 v in 7 v in 79 sg3 sg2 sg1 5mhz 5mhz 5mhz 1vp-p 714mvp-p 1vp-p t27 t25 t27 01011000 00000000 output drive capacity 1 (secondary distortion) (with lpf) h23 h25 h27 h29 v in 11 v in 9 v in 1 v in 73 sg9 sg9 sg1 sg9 5mhz 5mhz 5mhz 5mhz 700mvp-p 700mvp-p 1vp-p 700mvp-p t23 t25 t27 t29 connect the load of 1k to the output via c connection and measure the secondary distortion of output. -45 -35 db 330 0 0 3.5 00111100 00000000 01001010 00000000 c.sync output h voltage v36h v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t36 connect 10k between this output and v cc . 4.75 5 5.25 v 0 0 3.5 01001000 00000000 01001010 00000000 c.sync output l voltage v36l v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t36 connect 10k between this output and v cc . 0 0.3 0.6 v 0 0 3.5 01001000 00000000 01001010 00000000 c.sync2 output h voltage v37h v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t37 connect 10k between this output and v cc . 4.75 5 5.25 v 0 0 3.5 01001000 00000000 01001010 00000000 c.sync2 output l voltage v37l v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t37 connect 10k between this output and v cc . 0 0.3 0.6 v 0 0 3.5 01001000 00000000 continued on next page. LA73033M no.a0646-5/24
continued from preceding page. input signal out spec control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit r1 v18 v38 v30, v35 sw1 sw2 01001010 00000000 c.sync output pulse width w36 v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t36 output pulse width 3.2 4.2 5.2 s 0 0 3.5 01001000 00000000 01001010 00000000 c.sync threshold level w36v v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t36 the value of input sync at which the output pulse width becomes 1.3-folds or more as the input sync is reduced. 7.5 11.5 15.5 ire 0 0 3.5 01001000 00000000 (note) the c. sync2 threshold level is 12 ire at 6db and 12.8 ire at 0db . design guarantee items input signal out spec control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit r1 v18 v38 v30, v35 sw1 sw2 01011010 00000000 dg23 dg27 v in 13 v in 79 sg7 sg7 3.58mhz 3.58mhz 1vp-p 1vp-p t27 t27 ratio of the amplitude on the white level relative to that on the black level. -2 1 2 % 3.5 01011000 00000000 va23m 01011010 10000000 dg adg23 adg27 v in 13 v in 79 sg7 sg7 3.58mhz 3.58mhz 1vp-p 1vp-p t27 t27 when agc amplifier is used -2 1 2 % 1k 0 0 va27m 01011000 10000000 01011010 00000000 dp23 dp27 v in 13 v in 79 sg7 sg7 3.58mhz 3.58mhz 1vp-p 1vp-p t27 t27 difference of the phase on the white level relative to that on the black level -1 1 1.5 deg 3.5 01011000 00000000 va23m 01011010 10000000 dp adp23 adp27 v in 13 v in 79 sg7 sg7 3.58mhz 3.58mhz 1vp-p 1vp-p t27 t27 when agc amplifier is used -1 1.2 2 deg 1k 0 0 va27m 01011000 10000000 ct23 v in 13 v in 15 sg5 sg5 1vp-p 1vp-p t27 -60 -55 db 330 0 0 3.5 01001010 00000000 ct25 v in 7 v in 5 sg2 sg2 4mhz 4mhz 714mvp-p 714mvp-p t25 -60 -55 db 330 0 0 3.5 01000100 00000000 crosstalk ct27 v in 79 v in 77 sg5 sg5 1vp-p 1vp-p t27 the magnitude of crosstalk in which the non-selected input signal is carried on the selected signal output is specified by the value of selected signal output. -60 -55 db 330 0 0 3.5 01001000 00000000 01001010 00000000 video s/ n ratio sn23 sn27 v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t27 t27 s/ n in the hpf100khz and lpf 10mhz bands is expressed in db. -70 -65 db 330 0 0 3.5 01001000 00000000 01011010 00000000 video s/ n ratio (with lpf) sn23 sn27 v in 13 v in 79 sg5 sg5 1vp-p 1vp-p t27 t27 s/ n in the hpf100khz and lpf 10mhz bands is expressed in db. -65 -60 db 1k 0 0 3.5 01011000 00000000 LA73033M no.a0646-6/24
electrical characteristics at ta=25 c, unless otherwise specified v cc = 5.0v spec sw input signal out control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit v18 v38 s68, s65, s63 s60, s58, s56 dv1 dv2 current drain 2 i cc 21 v cc 2 current flowing through v cc 2 at no signal 64 80 96 ma 0 0 on on 00000000 00110000 current drain at rgb standby 2 i cc 23 v cc 2 current flowing through v cc 2 at ext-rgb control 18 22 26 ma 3 3 on on g68l g65l g63l v in 39 v in 41 v in 43 sg3 sg2 sg1 1vp-p 714mvp-p 1vp-p t68 t65 t63 gain at 6db for two drives g60l g58l g56l v in 45 v in 51 v in 53 sg5 sg6 sg6 1vp-p 1vp-p 1vp-p t60 t58 t56 measure gain of each output relative to input 5.6 5.9 6.4 db 0 0 on on 00000000 00110000 g68h g65h g63h v in 39 v in 41 v in 43 sg3 sg2 sg1 709mvp-p 507mvp-p 709mvp-p t68 t65 t63 gain at 9db for two drives g60h g58h g56h v in 45 v in 51 v in 53 sg5 sg6 sg6 709mvp-p 709mvp-p 709mvp-p t60 t58 t56 measure gain of each output relative to input 8.55 8.9 9.45 db 0 0 on on 00000000 11110000 g68l g65l g63l v in 39 v in 41 v in 43 sg3 sg2 sg1 1vp-p 714mvp-p 1vp-p t68 t65 t63 gain at 6db for one drive in two-drive mode g60l g58l g56l v in 45 v in 51 v in 53 sg5 sg6 sg6 1vp-p 1vp-p 1vp-p t60 t58 t56 measure gain of each output relative to input 5.6 6.1 6.4 db 0 0 off on 00000000 00110000 g68h g65h g63h v in 39 v in 41 v in 43 sg3 sg2 sg1 709mvp-p 507mvp-p 709mvp-p t68 t65 t63 gain at 9db for one drive in two-drive mode g60h g58h g56h v in 45 v in 51 v in 53 sg5 sg6 sg6 709mvp-p 709mvp-p 709mvp-p t60 t58 t56 measure gain of each output relative to input 8.55 9.1 9.45 db 0 0 on off 00000000 11110000 output gain ratio (composite/ s) 68/65 68/63 65/63 v in 39 v in 41 v in 43 sg3 sg2 sg1 709mvp-p 507mvp-p 709mvp-p t68 t65 t63 calculate the gain ratio of two outputs. -5 0 5 % 0 0 on on 00000000 11110000 continued on next page. LA73033M no.a0646-7/24
continued from preceding page. spec sw input signal out control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit v18 v38 s68, s65, s63 s60, s58, s56 dv1 dv2 output gain ratio (component) 60/58 60/56 58/56 v in 45 v in 51 v in 53 sg5 sg6 sg6 709mvp-p 709mvp-p 709mvp-p t60 t58 t56 calculate the gain ratio of two outputs. -5 0 5 % 0 0 on on 00000000 11110000 v in 39 v in 41 v in 43 sg3 sg2 sg1 7mhz 7mhz 7mhz 1vp-p 714mvp-p 1vp-p t68 t65 t63 7mhz change rate for f characteristics of gain f68l f65l f63l f60l1 f58l1 f56l1 v in 45 v in 51 v in 53 sg1 sg4 sg4 7mhz 7mhz 7mhz 1vp-p 1vp-p 1vp-p t60 t58 t56 measure gain of each output relative to input and calculate the change rate for gain at 100khz. -2 -0.8 0.4 db 0 0 on on 00000000 00110000 v in 39 v in 41 v in 43 sg3 sg2 sg1 27mhz 27mhz 27mhz 1vp-p 714mvp-p 1vp-p t68 t65 t63 27mhz change rate of f characteristics of gain f68h f65h f63h f60h1 f58h1 f56h1 v in 45 v in 51 v in 53 sg1 sg4 sg4 27mhz 27mhz 27mhz 1vp-p 1vp-p 1vp-p t60 t58 t56 measure gain of each output relative to input and calculate the change rate for gain at 100khz. -33 -25 db 0 0 on on 00000000 00110000 14mhz change rate for f characteristics of gain f60l2 f58l2 f56l2 v in 45 v in 51 v in 53 sg1 sg4 sg4 14mhz 14mhz 14mhz 1vp-p 1vp-p 1vp-p t60 t58 t56 -2.3 -1.1 0.1 db 0 0 on on 00001000 00110000 54mhz change rate for f characteristics of gain f60h2 f58h2 f56h2 v in 45 v in 51 v in 53 sg1 sg4 sg4 54mhz 54mhz 54mhz 1vp-p 1vp-p 1vp-p t60 t58 t56 measure gain of each output relative to input and calculate the change rate for gain at 100khz. -37 -30 db 00001000 00110000 gain at rgb through one drive g60e g58e g56e v in 9 v in 11 v in 73 sg8 sg8 sg8 700mvp-p 700mvp-p 700mvp-p t60 t58 t56 measure gain of each output relative to input. two-drive mode. 5.6 6.1 6.4 db 0 3 on off 10000000 00100000 10mhz change rate for f characteristics of gain at rgb through f60e f58e f56e v in 9 v in 11 v in 73 sg9 sg9 sg9 10mhz 10mhz 10mhz 700mvp-p 700mvp-p 700mvp-p t60 t58 t56 measure gain of each output relative to input and calculate the change rate for gain at 100khz. -0.5 -0.1 0.5 db 0 3 on off 10000000 00100000 gain at rgb standby one drive g60e g58e g56e v in 9 v in 11 v in 73 sg8 sg8 sg8 700mvp-p 700mvp-p 700mvp-p t60 t58 t56 measure gain of each output relative to input. 5.6 5.9 6.4 db 3 3 on off continued on next page. LA73033M no.a0646-8/24
continued from preceding page. spec sw input signal out control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit v18 v38 s68, s65, s63 s60, s58, s56 dv1 dv2 v65md v63md t65 t63 00000010 00110000 00000001 00110000 mute voltage v60md v58md v56md t60 t58 t56 measure the pin voltage. 2.1 2.5 2.9 v 0 0 on on 00000100 00110000 dc for sq vsq t66 4.1 4.4 4.7 v 0 0 on on 00100000 00110000 dc for lb vlb t66 2.05 2.2 2.35 v 0 0 on on 00010000 00110000 dc for 4 : 3 v43 t66 measure the pin voltage with v cc = 4.75 to 5.25v 0 0 0.35 v 0 0 on on 00000000 00110000 design guarantee items spec sw input signal out control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit v18 v38 s68, s65, s63 s60, s58, s56 dv1 dv2 gd68 gd65 gd63 v in 39 v in 41 v in 43 sg3 sg2 sg1 7mhz 7mhz 7mhz 1vp-p 714mvp-p 1vp-p t68 t65 t63 f characteristcs of group delay at 7mhz (interlace) gd60-1 gd58-1 gd56-1 v in 45 v in 51 v in 53 sg1 sg4 sg4 7mhz 7mhz 7mhz 1vp-p 714mvp-p 714mvp-p t60 t58 t56 difference in group delay of 7mhz relative to 100khz of each output -20 10 20 ns 0 0 on on 00000000 00110000 f characteristics of group delay at 14mhz (progressive) gd60-2 gd58-2 gd56-2 v in 45 v in 51 v in 53 sg1 sg4 sg4 14mhz 14mhz 14mhz 1vp-p 714mvp-p 714mvp-p t60 t58 t56 difference in group delay of 14mhz from 100khz of each output -15 5 15 ns 0 0 on on 00001000 00110000 dg68 dg63 dg60 v in 39 v in 43 v in 45 sg7 sg7 sg7 3.58mhz 3.58mhz 3.58mhz 1vp-p 1vp-p 1vp-p t68 t63 t60 00000000 00110000 dg dgmix v in 41 v in 43 sg2 sg7 3.58mhz y only component 286mvp-p 1vp-p t68 calculate the ratio in percentage of the amplitude of sin wave on the white level relative to that of sin wave on the black level of each output signal. 1 2 % 0 0 on on 01000000 00110000 continued on next page. LA73033M no.a0646-9/24
continued from preceding page. spec sw input signal out control voltage i 2 c bus data (msb-lsb) parameter symbol point signal freq mag point test condition min typ max unit v18 v38 s68, s65, s63 s60, s58, s56 dv1 dv2 dp68 dp63 dp60 v in 39 v in 43 v in 45 sg7 sg7 sg7 3.58mhz 3.58mhz 3.58mhz 1vp-p 1vp-p 1vp-p t68 t63 t60 00000000 00110000 dp dpmix v in 41 v in 43 sg2 sg7 3.58mhz y only component 286mvp-p 1vp-p t68 measure the difference in phase of the sin wave on the black level of each output signal relative to that of sin wave on the white level. -1 0.5 1 deg 0 0 on on 01000000 00110000 v in 39 v in 41 v in 43 sg3 sg2 sg1 4mhz 4mhz 4mhz 1vp-p 714mvp-p 1vp-p t68 t65 t63 crosstalk ct68 ct65 ct63 ct60 ct58 ct56 v in 45 v in 51 v in 53 sg1 sg4 sg4 4mhz 4mhz 4mhz 1vp-p 714mvp-p 714mvp-p t60 t58 t56 measure the 4mhz co mponent of the otput of non-input route and calculate its ratio relative to the 4mhz amplitude of other outputs. -60 -55 db 0 0 on on 00000000 00110000 sn68 sn63 sn60 v in 39 v in 43 v in 45 sg5 sg5 sg5 1vp-p 1vp-p 1vp-p t68 t63 t60 -79 -77 db 0 0 on on 00000000 00110000 video s/ n ratio snmix v in 43 sg5 1vp-p t68 measure the s/ n ratio of output signal with a noise meter (lpf 10mhz, hpf 100khz) and express it in db. -73 -71 db 0 0 on on 01000000 00110000 LA73033M no.a0646-10/24
LA73033M no.a0646-11/24 block diagram and test circuits + + gnd (cn2) gnd (cn3) gnd (cs2) y1.out + gnd (cs4) cv.out/y.out + c.out 10k v cc (cn2) v cc (b) gnd (ic) gnd (b) gnd (y) gnd (c) gnd (cv) b_out agcctl1 agcctl2 ext-rgb_sw csync2.out csync.out sclk sdata v cc (ic) y.out/cv.out c.out/cr.out/r.out cv.out/cb.out/g.ou t v cc (y) v cc (c) v cc (sy) v cc (cv) gnd (sy) stand.by b.in y4.in y3.in y2.in y.in/cv.in c4.in n.c n.c n.c n.c c3.in c2.in cr.in/r.in cb.in/g.in cv2.in cv3.in cv4.in cv5.in + gnd (cn1) gnd (cn4) pedestal clamp pedestal clamp clamp sync sep 6db/9db amp gnd (cs1) v cc (cn1) v cc (cn2) v cc (cs1) n.c n.c n.c n.c n.c cb.in/b.in y2.out/r out/c.out + cr.out/g.out gnd (cn3) + cb.out/b.out y2.in/r.in y.in c.in cr.in/g.in + cv6.in cv.in n.c n.c n.c n.c n.c 75 driver lpf1 lpf2 pedestal clamp clamp 6db/9db amp 75 driver pedestal clamp clamp pedestal clamp clamp pedestal clamp clamp lpf1 lpf2 6db/9db amp clamp 75 driver lpf1 lpf2 clamp reg2 6db/9db amp clamp ctl logic serial decorder v.sep 75 driver lpf1 lpf1 lpf1 6db/9db amp y/c mix pedestal clamp synctip clamp sync sep lpf lpf 75 driver 6db/9db amp 0db/6db amp sync select synctip clamp synctip clamp synctip clamp synctip clamp synctip clamp sync lpf sync sep agcamp 0db/3db 75 driver 6db amp 6db amp s1/s2 pc_out 0db/6db amp 0db/6db amp clp pulse gen 6db amp lpf reg1 lpf 0db/6db amp sync select synctip clamp synctip clamp synctip clamp synctip clamp sync lpf sync sep agcamp 0db/3db 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LA73033M no.a0646-12/24 pin functions pin no. pin name i/0 impe dance dc voltage pin explanation input/output form 13 cv2.in 15 cv3.in 17 cv4.in 19 cv5.in 21 cv6.in 1 y1.in / cv.in 79 y2.in 77 y3.in 75 y4.in i clamp form 1.5v at 0db 2.1v at 6db 1.5v at agc 1.5v at no selection 1.5v at no signal cs-rec : 1.5v recommended clamp capacitor = 0.1 f. for the selected pin, keyed clamp is applied to the input so that the clamp voltage of the output signal becomes constant when the signal is provided. diode clamp is applied to the input when there is no signal. when no pin is selected and at cs-rec, diode clamp is applied to the input regardless of whether or not the signal is provided. v cc v cc 50 f 100k 200 19k in v cc v cc v cc clamp pulse 0.5 a clamp pulse 7 c2.in 5 c3.in 3 c4.in i 10k 2.9v recommended capacitor = 0.1 f. dc is overlapped over the signal through external c connection regardless of whether there is a signal or the pin is selected or amp-gain in the mode other than cs-rec. 10k 200 v cc v cc 50 f in 100 f v cc 11 cb.in g.in 9 cr.in r.in 73 b.in i clamp form for component 3.2v at 0db 3.0v at 6db for rgb 2.2v at 0db 2.5v at 6db for rgb through 2.3v 1.2v at no selection 1.2v at no signal to pin 1 recommended clamp capacitor = 0.1 f. for the selected signal, keyed clamp is applied to the input so that the clamp voltage of output signal becomes constant when there is a signal to pin 1. diode clamp is applied to the input when there is no signal at pin 1 or when the pin is not selected. for rgb through, feedback clamp is applied from the output to the input. 200 v cc v cc 50 f 100k 19k in v cc v cc v cc clamp pulse 0.5 a clamp pulse 23 cv.out cb.out g.out 25 c.out cr.out r.out 27 y.out cv.out 29 b.out o 4.5 0.8v for cv/ y 2.5v for component 1.25v for rgb for chroma output 2.2v at 0db 2.4v at 6db the signal that has been selected and keyed clamped (excluding chroma) is amplified and output from the emitter follower. the constant curre nt of emitter follower is 2.5ma when the built-in lpf is selected and 7.5ma when it is not selected. 40 v cc ou t v cc continued on next page.
LA73033M no.a0646-13/24 continued from preceding page. pin no. pin name i/0 impe dance dc voltage pin explanation input/output form 18 stand -by-sw 38 ext -rgb -sw i 17g hi : 3.3v lo : 0v normal mode when pins 18 and 38 are ?l.? rgb through mode when pin 18 is ?l? and pin 38 is ?h.? rgb standby mode when pins 18 and 38 are ?h.? cs-rec mode when pin 18 is ?h? and pin 38 is ?l.? v cc 50k 8k 100 f in 20 sw-reg -filt 40 dv-reg -filt o 880 with pin 18 = l, pin 20 : 2.5v pin 40 : 2.0v 1with pin 18 = h, pin 20 : 0v pin 40 : 0v output pin for regulator voltage in ic. s/ n improvement measures recommended by inserting a capacitor of about 470 f between this pin and gnd. the amplifier reference voltage on the sw side is based on the regulator voltage of pin 20 and that on the driver side is based on the regulator voltage of pin 40. 10k 10k 12k 10pf v cc ou t v cc 30 agcctl1 (cv) 35 agcctl2 (y) i 128m hi : 5v lo : 2v center : 3.3v pin to control gain of composite and y signals when agc-amp is used. to suppress crosstalk, it is recommended to insert a noise suppressing capacitor near the pin between the pin and gnd. 500 v cc 20 f in v cc 36 c.sync out 37 c.sync out2 i 480 hi : 5v lo : 0.3v composite sink output pin lo (sink) at sync pin 36 can be used for detection of no-signal because lpf is applied. pin 37 is for detection of the weak electric field. pin 37 can be changed to v.sync-out. 300 10k v cc out ext.res. continued on next page.
LA73033M no.a0646-14/24 continued from preceding page. pin no. pin name i/0 impe dance dc voltage pin explanation input/output form 72 v cc (b) v cc for pin 73 input 74 v cc (y) v cc for input of pins 1, 79, 77, and 75 8 v cc (c) v cc for input of pins 9, 7, 5, and 3 10 v cc (sy) v cc for input of pins 11, 13, 15, 17, 19, and 21 12 v cc (cv) p 5v description of each pin v cc on the input sw. to avoid crosstalk, it is recommended to insert a capacitor between each v cc and gnd. keep v cc always on. v cc for sync-sep, clamp pulse 14 gnd (sy) gnd for pin 73 input 22 gnd (cv) gnd for input of pins 1, 79, 77, and 75 24 gnd (c) gnd for input of pins 9, 7, 5, and 3 26 gnd (y) gnd for pins 11, 13, 15, 17, 19, and 21 28 gnd (b) p 0v description of each pin gnd on the input sw side gnd for sync-sep, clamp pulse 76 nc 78 nc 80 nc 2 nc 4 nc 6 nc 16 nc 0v nc pins on the input sw side. it is recommended to connect this to gnd on the substrate to avoid interference between input signals. 32 sdata 33 sclk i 734m hi : 5v lo : v pin to enter the serial data and its clock for iic bus. for the input waveform, refer to the sda & scl standard. in 500 v cc 25 a 39 cv.in 43 y1.in 45 y2.in r.in i clamp form 2.2v at 6db 2.3v at 9db 1.85v at no signal recommended capacitor = 0.1 f. for the signal with input, feedback clamp is applied to the input so that the clamp voltage becomes constant. for signal without input, diode clamp is applied to the input. pins 39 and 45 drop to 0 to 1v when not selected. 200 v cc v cc 100 f 100k 19k in v cc v cc continued on next page.
LA73033M no.a0646-15/24 continued from preceding page. pin no. pin name i/0 impe dance dc voltage pin explanation input/output form 41 c.in i 10k 2.7v recommended capacitor = 0.1 f. dc is overlapped over the signal with external c connected, regardless of the signal or no-signal and amp-gain. v cc 150 f in 100 f v cc v cc v cc 200 10k 51 cr.in g.in 53 cb.in b.in i clamp form for component 2.8v at 6db 2.7v at 9db for rgb 2.2v at 6db 2.3 at 9db 1.85v at no signal recommended capacitor = 0.1 f. in the component mode, keyed clamp is applied to the input so that the pedestal of output signal becomes constant when there is a signal at pin 45. in the rgb mode, feedback clamp is applied to the input so that the output signal clamp voltage becomes constant. diode clamp is applied to the input when there is no signal. 200 v cc v cc 100k 19k in v cc v cc v cc clamp pulse clamp pulse 68 cv.out y1.out 65 c.out 63 y1.out 60 y2.out r.out c.out 58 cr.out g.out 56 cb.out b.out o 4 1.3v for cv/ y/ rgb 2.5v for component for chroma output 2.4v at 0db 2.6v at 6db recommended coupling capacitor = 470 f (0.1 f for chroma). the signal that has passed amp & lpf is output from the 75 driver. two drives possible. it is recommended to provide this capacitor as near as possible to the pin to avoid interference. 30 30 v cc ou t v cc 66 c_dc out o 11 hi : 4.4v mid : 2.2v lo : 0v circuit to output the dc voltage of s1 and s2 standards. when using this pin, insert a resistor (driving with about 10 k per drive) between the output chroma signal after coupling and this pin, so that the dc voltage of s1 and s2 standard can be overlapped. v cc 100 f 300 f 500 500 1k 100k 500 v cc out v cc 34 v cc (ic) v cc for input of pins 32 and 33 44 v cc (cs1) v cc for input of pins 39, 41, and 43 50 v cc (cn1) v cc for input of pins 45, 51, and 53 55 v cc (cn2) v cc for output of pins 60, 58, and 56 62 v cc (cs2) p 5v description of each pin v cc on the output driver side. it is recommended to insert a capacitor between each v cc and gnd to avoid crosstalk. keep v cc normally on. v cc for output of pins 68, 65, and 63 continued on next page.
LA73033M no.a0646-16/24 continued from preceding page. pin no. pin name i/0 impe dance dc voltage pin explanation input/output form 31 gnd (ic) gnd for input of pins 32 and 33 42 gnd (cs1) gnd for input of pins 39, 41, and 43 52 gnd (cn1) gnd for input of 45, 51, and 53 57 gnd (cn3) p 0v description of each pin gnd on the output driver side gnd for output of pin 56 59 gnd (cn4) gnd for output of pin 58 61 gnd (cn2) gnd for output of pins 60 64 gnd (cs3) gnd for output of pins 63 67 gnd (cs2) gnd for output of pin 65 69 gnd (cs4) gnd for output of pin 68 46 nc 47 nc 48 nc 49 nc 54 nc 70 nc 71 nc 0v nc pins on the output driver side. it is recommended to connect this pin to gnd on the substrate to avoid interference with the input sw side.
LA73033M no.a0646-17/24 device address gr address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) sw1 00000001 insel3 insel2 insel1 lpf sw gain1 swgain2 yout sel *res sw2 00000010 agc v.sync *res *res clpoff1 clpiup test2 test1 dr1 00000011 scart yc mix cdc2 cdc1 prog gb mute yc mute cp mute dr2 00000100 cv/ s gain cp gain cv/ s drive cp drive scart yc *res *res clpoff2 * res means a reserved bit. initial state sw block insel3 insel2 insel1 input selection mode 0 0 0 in1 component 0 0 1 in1 rgb 0 1 0 in2 composite/ s 0 1 1 in3 composite/ s 1 0 0 in4 composite/ s 1 0 1 in5 composite/ s 1 1 0 in6 composite/ s insel3 insel2 insel1 sw block input selection/mode changeover 1 1 1 prohibition lpf sw block lpf 1 : lpf on 0 : lpf off swgain1 sw block amplifier gain changeover 1 (for composite/ y signal) 1 : +6db (agc used+3db) 0 : 0db swgain2 sw block amplifier gain changeover 2 (c/ component/ rgb signal) 1 : +6db (agc used+3db) 0 : 0db yout sel sw block yout output selection 1 : composite 0 : y agc sw block agc on/off 1 : on 0 : off v.sync sync output changeover 1 : v-sync output 0 : c- sync output (for detection of weak field) clpoff1 test mode (sw block input clamp off) 1 : clamp off 0 : clamp on clpiup increase in sw block clamp current 1 : increase in the clamp current 0 : clamp current normal test2 00 : c-sync (normal) 01 : clamp pulse test1 c-sync output (test mode) 10 : prohibition 11 : macro vision gate driver block scart driver block component m ode changeover 1 : scart (rgb) 0 : y/ cb/ cr yc mix driver block composite output selection 1 : y/ c mix 0 : composite (y/ c mix off) cdc2 00 : low (0v) 4 : 3mode 01 : middle (2.2v) letter box cdc1 driver block c_dc output voltage 10 : high (5v) squeeze 11 : prohibition prog driver block lpf changeover 1 : progressive 0 : interlace gb mute driver block g/b mute 1 : mute on 0 : mute off yc mute driver block yc mute 1 : mute on 0 : mute off cp mute driver block component mute 1 : mute on 0 : mute off cv/ s gain driver block composite/ s amplifier gain 1 : +9db 0 : +6db cp gain driver block component amplifier gain 1 : +9db 0 : +6db cv/ s drive driver block compos ite/ s output drive capacity 1 : two-system drive 0 : one-system drive cp drive driver block component output drive capacity 1 : two-system drive 0 : one-system drive scart yc driver block scart yc mode changeover 1 : yc 0 : rgb clpoff2 test mode (driver block input clamp off) 1 : clamp off 0 : clamp on *initial setting at power on gr address data sw1 00000001 01100010 sw2 00000010 00000000 dr1 00000011 01000000 dr2 00000100 00110000
LA73033M no.a0646-18/24 control pin function table (1) *for the serial control pin, enter 3.5 to 5v for h and 0 to 1.5v for l. *for the parallel control pin, enter 2.6 to 5v for h and 0 to 0.7v for l. *for all control pins, do not apply the voltage higher than the one applied to v cc or lower than the one applied to gnd. *no control pin must be used in the open state. *values in the table are standard values. fo r spec, refer to the electrical characteristics. [selection of the sw side input signal] signal to be output control gr address 00000001 gr address 00000010 pin 18 standby pin 38 rgb through input pin to be selected pin 23 pin 25 pin 27 pin 29 cv (rear 1) 010***1* ****0*00 l h/ l 13 (cv) , 7 (c) (cv) c cv dc s (rear 1) 010***0* ****0*00 l h/ l 7 (c) , 79 (y) - c y dc cv (rear 2) 011***1* ****0*00 l h/ l 15 (cv) , 5 (c) (cv) c cv dc s (rear 2) 011***0* ****0*00 l h/ l 5 (c) , 77 (y) - c y dc cv (front) 100***1* ****0*00 l h/ l 17 (cv) , 3 (c) (cv) c cv dc s (front) 100***0* **** 0*00 l h/ l 3 (c) , 75 (y) - c y dc 101***1* ****0*00 l h/ l 19 (cv) (cv) dc cv dc cv (tuner) 101***0* ****0*00 l h/ l none - dc dc dc 110***1* ****0*00 l h/ l 21 (cv) (cv) dc cv dc cv (tuner) 110***0* ****0*00 l h/ l none - dc dc dc 000***** ****0*00 l l 1 1(cb) , 9 (cr) , 1 (y) cb cr y dc component 000***** ****0*00 l h 1 (y) - - y - 001***** ****0*00 l l 11 (g) , 9 (r) , 1 (cv) , 73 (b) g r cv b rgb 001***** ****0*00 l h 1 (cv) - - cv - ******** ******** h l pin 15 input 15 (cv) - - - - ******** ******** h l pins 15+77 input 77 (y) - - - - cs-rec ******** ******** h l pin 77 input 77 (y) - - - - (note 1) (cv) : though a signal is output, its use is not recommended. (note 2) dc : the dc voltage differing depending on the amp-gain setting is output. (note 3) - : either the signal is not output or should not be used because the dc voltage is abnormal if output. [selection of the input signal for c.sync out] signal to be output control gr address 00000001 gr address 00000010 pin 18 standby pin 38 rgb through input pin to be selected c.sync c.sync2 cv (rear 1) 010***1* *0**0*00 l h/ l 13 (cv) c.sync c.sync2 s (rear 1) 010***0* *0**0*00 l h/ l 79 (y) c.sync c.sync2 cv (rear 2) 011***1* *0**0*00 l h/ l 15 (cv) c.sync c.sync2 s (rear 2) 011***0* *0**0*00 l h/ l 77 (y) c.sync c.sync2 cv (front) 100***1* *0**0*00 l h/ l 17 (cv) c.sync c.sync2 s (front) 100***0* *0**0*00 l h/ l 75 (y) c.sync c.sync2 101***1* *0**0*00 l h/ l 19 (cv) c.sync c.sync2 cv (tuner) 101***0* *0**0*00 l h/ l none 110***1* *0**0*00 l h/ l 21 (cv) c.sync c.sync2 cv (tuner) 110***0* *0**0*00 l h/ l none component 000***** *0**0*00 l h/ l 1 (y) c.sync c.sync2 rgb 001***** *0**0*00 l h/ l 1 (cv) c.sync c.sync2 v.sync ******** *1**0*00 l h/ l same as above c.sync v.sync ******** *0**0*01 l h/ l same as above clamp pulse c.sync2 monitor ******** *0**0*11 l h/l same as above macro gate pulse c.sync2 ******** ******** h l pin 15 input 15 (cv) c.sync ******** ******** h l pins 15 + 77 input 77 (y) c.sync cs-rec ******** ******** h l pin 77 input 77 (y) c.sync rgb standby ******** ******** h h 1 (cv) c.sync
LA73033M no.a0646-19/24 control pin function table (2) [sw side amp-gain selection] amp-gain control gr address 00000001 gr address 00000010 pin 18 standby pin 38 rgb through pin 23 pin 25 pin 27 pin 29 ****00** 0***0*00 l h/ l (fixed at 0db) fixed at 0db fixed at 0db dc ****10** 0***0*00 l h/ l (fixed at 6db) fixed at 0db fixed at 6db dc ****01** 0***0*00 l h/ l (fixed at 0db) fixed at 6db fixed at 0db dc ****11** 0***0*00 l h/ l (fixed at 6db) fixed at 6db fixed at 6db dc ****00** 1***0*00 l h/ l (agc 0db) fixed at 0db agc0db dc ****10** 1***0*00 l h/ l (agc 3db) fixed at 0db agc3db dc ****01** 1***0*00 l h/ l (agc 0db) fixed at 6db agc0db dc cv/ s ****11** 1***0*00 l h/ l (agc 3db) fixed at 6db agc3db dc 000*00** 0***0*00 l h/ l fixed at 0db fixed at 0db fixed at 0db dc 000*10** 0***0*00 l h/ l fixed at 0db fixed at 0db fixed at 6db dc 000*01** 0***0*00 l h/ l fixed at 6db fixed at 6db fixed at 0db dc 000*11** 0***0*00 l h/ l fixed at 6db fixed at 6db fixed at 6db dc 000*00** 1***0*00 l h/ l fixed at 0db fixed at 0db agc0db dc 000*10** 1***0*00 l h/ l fixed at 0db fixed at 0db agc3db dc 000*01** 1***0*00 l h/ l fixed at 6db fixed at 6db agc0db dc component 000*11** 1***0*00 l h/ l fixed at 6db fixed at 6db agc3db dc 001*00** 0***0*00 l h/ l fixed at 0db fixed at 0db fixed at 0db fixed at 0db 001*10** 0***0*00 l h/ l fixed at 0db fixed at 0db fixed at 6db fixed at 0db 001*01** 0***0*00 l h/ l fixed at 6db fixed at 6db fixed at 0db fixed at 6db 001*11** 0***0*00 l h/ l fixed at 6db fixed at 6db fixed at 6db fixed at 6db 001*00** 1***0*00 l h/ l fixed at 0db fixed at 0db agc0db fixed at 0db 001*10** 1***0*00 l h/ l fixed at 0db fixed at 0db agc3db fixed at 0db 001*01** 1***0*00 l h/ l fixed at 6db fixed at 6db agc0db fixed at 6db rgb 001*11** 1***0*00 l h/ l fixed at 6db fixed at 6db agc3db fixed at 6db (note 1) though a signal is output, its use is not recommended. (note 2) at the gr address = 0000 0001 of cv/s, *** does not contain 00* . [sw side lpf selection] lpf route of each output load corresponding to each output control gr address 00000001 gr address 00000010 pin 18 standby pin 38 rgb through pins 23, 25, 27, 29 pins 23, 25, 27, 29 lpf-on ***1**** ****0*00 l h/ l pass 1k lpf-off ***0**** ****0*00 l h/ l through 330
LA73033M no.a0646-20/24 control pin function table (3) [driver side input signal selection] signal to be output control gr address 00000011 gr address 00000100 pin 18 standby pin 38 rgb through input pin to be selected pin 68 pin 65 pin 63 pin 60 pin 58 pin 56 00***000 ****0**0 l l 39 (cv) 41 (c) 43 (y1) 45 (y2) 51 (cr) 53 (cb) cv c y1 y2 cr cb 00***010 ****0**0 l l 39 (c v) 45 (y2) 51 (cr) 53 (cb) cv dc dc y2 cr cb cv/ s component 00***001 ****0**0 l l 39 (cv) 41 (c) 43 (y1) cv c y1 dc dc dc 01***000 ****0**0 l l 41 (c) 43 (y1) 45 (y2) 51 (cr) 53 (cb) cv c y1 y2 cr cb 01***010 ****0**0 l l 41 (c) 43 (y1) 45 (y2) 51 (cr) 53 (cb) cv dc dc y2 cr cb y/ c-mix component 01***001 ****0**0 l l 39 (cv) 41 (c) 43 (y1) cv c y1 dc dc dc 10***000 ****0**0 l l 39 (c v) 41 (c) 43 (y1) 45 (r) 51 (g) 53 (b) cv c y1 r g b 10***010 ****0**0 l l 39 (cv) 45 (r) 51 (g) 53 (b) cv dc dc r g b cv/ s rgb 10***001 ****0**0 l l 39 (cv) 41 (c) 43 (y1) cv c y1 dc dc dc 11***000 ****0**0 l l 41 (c) 43 (y1) 45 (r) 51 (g) 53 (b) cv c y1 r g b 11***010 ****0**0 l l 41 (c) 43 (y1) 45 (r) 51 (g) 53 (b) cv dc dc r g b yc/ mix rgb 11***001 ****0**0 l l 39 (cv) 41 (c) 43 (y1) cv c y1 dc dc dc 10***000 ****1**0 l l 41 (c) 43 (y1) 51 (g) 53 (b) y1 c y1 c g r 10***010 ****1**0 l l 41 (c) 43 (y1) 51 (g) 53 (b) y1 dc dc c g r scart y/ c 10***100 ****1**0 l l 41 (c) 43 (y1) y1 c y1 c dc dc 11***000 ****1**0 l l 41 (c) 43 (y1) 51 (g) 53 (b) cv c y1 c g r 11***010 ****1**0 l l 41 (c) 43 (y1) 51 (g) 53 (b) cv dc dc c g r scart y/ c-mix 11***100 ****1**0 l l 41 (c) 43 (y1) cv c y1 c dc dc *0****0* ****0**0 l h 39 (cv) 41 (c) 43 (y 1) 9 (r) 11 (g) 73 (b) cv c y1 r g b cv/ s rgb through *0****1* ****0**0 l h 39 (cv) 9 (r) 11 (g) 73 (b) cv dc dc r g b *0****0* ****1**0 l h 41 (c) 43 (y1) 9 (r) 11 (g) 73 (b) y1 c y1 r g b scart y/ c rgb through *0****1* ****1**0 l h 43 (y1) 9 (r) 11 (g) 73 (b) y1 dc dc r g b *1****0* *******0 l h 41 (c) 43 (y1) 9 (r) 11 (g) 73 (b) cv c y1 r g b y/ c-mix rgb through *1****1* *******0 l h 41 (c) 43 (y1) 9 (r) 11 (g) 73 (b) cv dc dc r g b rgb standby ******** ******** h h 9 (r) 11 (g) 73 (b) - - - r g b cs-rec ******** ******** h l - - - - - - (note 1) y1 is a y signal for s and y2 is a y signal for component. (note 2) the mute voltage described in the ta ble of electrical characteristics is output. (note 3) -: either the signal is not output or should not be used because the dc voltage is abnormal if output.
LA73033M no.a0646-21/24 control pin function table (4) [driver side amp-gain selection] amp-gain control gr address 00000011 gr address 00000100 pin 18 standby pin 38 rgb through pin 68 pin 65 pin 63 pin 60 pin 58 pin 56 *****000 00****00 l l 6db 6db 6db 6db 6db 6db *****000 10****00 l l 9db 9db 9db 6db 6db 6db *****000 01****00 l l 6db 6db 6db 9db 9db 9db dac signal *****000 11****00 l l 9db 9db 9db 9db 9db 9db *****000 0*****00 l h 6db 6db 6db 6db 6db 6db dac signal rgb through *****000 1*****00 l h 9db 9db 9db 6db 6db 6db rgb standby ******** ****** ** h h - - - 6db 6db 6db (note 1) at scart-yc, the gain control of chroma output is different between pin 65 and pin 60. (note 2) -: either the signal is not output or should not be used because the dc voltage is abnormal if output. [driver side lpf selection] lpf cut-off frequency (mhz) control gr address 0000001 gr address 00000100 pin 18 standby pin 38 rgb through pin 68 pin 65 pin 63 pin 60 pin 58 pin 56 interlace ***1**** *** ***00 l l 9 9 9 9 9 9 progressive ***0**** ******00 l l 9 9 9 18 18 18 rgb through ******** ******00 l h 9 9 9 through through through rgb standby ******** ******** h h - - - through through through [selection of the number of channels that can be driven by 75 driver ] number of channels that can be driven of each output control gr address 0000001 gr address 00000100 pin 18 standby pin 38 rgb through pin 68 pin 65 pin 63 pin 60 pin 58 pin 56 *****000 **00***0 l l 1 1 1 1 1 1 *****000 **10***0 l l 2 2 2 1 1 1 *****000 **01***0 l l 1 1 1 2 2 2 dac signal *****000 **11***0 l l 2 2 2 2 2 2 ******0* **00***0 l h 1 1 1 1 1 1 ******0* **10***0 l h 2 2 2 1 1 1 ******0* **01***0 l h 1 1 1 2 2 2 dac signal rgb through ******0* **11***0 l h 2 2 2 2 2 2 rgb standby ******** ** ****** h h - - - 1 1 1 [selection of s1 and s2 overlapping dc] pin 66 control gr address 0000001 gr address 00000100 pin 18 standby pin 38 rgb through application output voltage (v) **00**** *******0 l h/ l for 4 : 3 0 **01**** *******0 l h/ l for letter box 2.2 **10**** ***** **0 l h/ l for squeeze 4.4 for s1 and s2 control **11**** *******0 l h/ l prohibited -
LA73033M no.a0646-22/24 test input signal p-p sin wave sg.1 sg.2 sg.3 sg.4 sg.5 sg.6 sg.7 sg.8 sg.9 140ire 40ire 1h p-p 100ire 1h p-p sin wave 100ire 1h p-p sin wave sin wave 140ire 40ire 40ire 40ire 100ire 50ire 1h 1h 1h 1h p-p 140ire p-p 1h 100ire p-p 1h 100ire p-p sin wave 140ire p-p
LA73033M no.a0646-23/24 sample application yout2 gndcn4 crout gndcn3 cbout v cc cn2 cb_in nc nc nc nc nc gndcn1 cr_in v cc cn1 y2_in v cc cs1 y1_in gndcs1 c_in regdv cv_in extrgbh sync2l sync_l agcctl2 LA73033M v cc ic scl sda gndic agcctl1 bout gndb yout gndy cout gndc cvout gndcv cv6_in + y1_in c4_in c3_in c2_in v cc c c1_in v cc sy cv1_in v cc cv cv2_in gndsy cv3_in nc nc nc nc cv4_in stdbyh cv5_in regsw gndcn2 v cc cs2 yout1 gndcs3 coutd c_dc gndcs2 cvout gndcs4 v cc b b1_in v cc y y4_in y3_in v cc 1 v cc 2 y2_in nc nc nc nc nc + + 75 v in 21 0.1 f 470 f t21 t20 v1 8 + 75 v in 19 0.1 f t19 + 75 v in 17 0.1 f t17 + 75 v in 15 0.1 f t15 + 75 v in 13 0.1 f t13 + 75 v in 11 0.1 f t11 + 75 v in 9 0.1 f t9 + 75 v in 7 0.1 f t7 + 75 v in 5 0.1 f t5 + + 75 v in 3 0.1 f t3 + 75 v in 53 0.1 f t53 + 75 v in 73 0.1 f 470 f 470 f 470 f 470 f 470 f 470 f t73 + 75 v in 75 0.1 f 0.1 f t75 + 75 v in 77 0.1 f t77 + 75 v in 79 0.1 f t79 + 75 v in 1 0.1 f t1 75 75 75 4.7k 75 s68 t68a + 75 75 75 75 s65 t65a + 470 f 10k + 100 f + 75 75 75 75 s63 t63a + 75 75 75 75 s60 t60a + 75 75 75 75 s58 t58a + 75 75 75 75 s56 t56a t66 t68 t65 t63 t60 t56 t58 v38 v35 v30 + + 75 v in 51 0.1 f t51 + 75 v in 45 0.1 f t45 + 75 v in 43 0.1 f t43 + 75 v in 41 0.1 f t41 + 75 v in 39 0.1 f t39 t40 + +5v + + t37 330 t29 100 f + 330 t27 100 f + 330 t25 100 f + 330 t23 10k +5v + t36 seria l data 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
LA73033M ps no.a0646-24/24 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of july, 2007. specifications and informat ion herein are subject to change without notice.

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